The present invention relates generally to high-speed data communication links and, more particularly, to improving equalization in a high-speed serializer-deserializer (SerDes).
System architectures such as Infiniband™ and PCI Express utilize high-speed serializer-deserializer (SerDes) links to transmit data packets across serial links. These architectures are migrating to SerDes links that support link speeds at single data rate (SDR), double data rate (DDR) and quad data rate (QDR). In doing so, each architecture is defining link-training methods that enable the link to support transmitting data at the higher data rates.
The Infiniband specification, Vol. 2, Rel. 1.2, supports adaptive equalization to compensate for signal distortion at the higher data rates. The Infiniband specification, section 5.6.4, Link Training State Machine, defines the procedure to enable adaptive equalization in an Infiniband system. The Link Training State Machine specification defines a 2 ms period to negotiate each side of a link's capabilities to support the SDR, DDR and QDR speeds. Once the negotiation process is completed, the Infiniband specification defines a 100 ms period to allow the default, or any of the 16 other possible (possibly available) adaptive equalization settings to be implemented across the entire link width, i.e., all of the link channels.
This solution is limited, however, in that one setting is selected for the entire link width (i.e., all of the channels). Link widths can be 1, 4, 8 and 12 channels wide using Infiniband, and up to 16 channels wide for PCI express. In an ideal system, every channel would be uniform and the above-mentioned method would be fine. In reality, however, this is hardly the case. That is, each medium or channel has it own set of impedance characteristics and tolerance. The Link Training State Machine method does not take into the account the varying characteristics between each channel. By limiting each channel to one set of adaptive equalization settings could mean that some of the channels will not work optimally at DDR/QDR rates. For example, at DDR/QDR speeds, real-time operation may find that only 8 channels out of the 12 available channels are operating effectively, which would result in significant performance degradation.
What would be desirable, therefore, is a new structure and process that allows for each channel within a high-speed SerDes architecture to be independently monitored and the channel's adaptive equalization setting modified where necessary.